I need to solve my homework for computer architecture and data structure.

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1. Given f (A, B, C) = Σ (0, 3, 5, 6, 7). Realize this function
a. as a two-level AND-OR network. Assume that the inverted versions of the inputs are
already available.
b. as a two-level OR-AND network. Assume that the inverted versions of the inputs are
already available.
c. as a NAND-only network based on the SOP expression for f
d. as a NOR-only network based on the POS expression for f
2. Consider a 3-bit ripple-carry adder (RCA) circuit. Assume that the sum of each
constituent full-adder of this RCA is obtained using a 3-bit XOR gate that has a
propagation delay of 3 ns. The carry-out bit of each individual full-adder is generated
using AND and OR gates. These gates have a delay of 2 ns and 2 ns, respectively. What
is the overall delay of this RCA?
3. Show the complete design of a 2-bit ALU whose functionality is described in the table
below. The ALU receives two 2-bit-wide data inputs, A and B. It also has two 1-bit-wide
function-control inputs S1 and S0. Depending on the value of S1S0, the ALU performs and
outputs one of the functions specified in the table below:
S1    S0        Function
0        0         ALU output = A
0        1         ALU output = A + B
1        0        ALU output = bitwise AND of A and B
1        1        ALU output = bitwise complement of A
4. Realize the function f (A, B, C) = A + BC using a decoder of the minimum possible size
and other logic gates, as necessary.
5. Design a full-subtractor using 4-to-1 multiplexers only. Assume that the inverted versions
of the full-subtractor inputs are already available.

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